Dynamic random access memory (DRAM) is a type of random m access memory that stores each bit of data in a separate capacitor. A simplest DRAM cell comprises a single N-type metal-oxide-semiconductor (NMOS) transistor and a single capacitor. If charge is stored in the capacitor, the cell is said to store a logic HIGH, depending on the convention used. If no charge is present, the cell is said to store a logic LOW. Because the charge in the capacitor dissipates over time, DRAM systems require additional refreshing circuitries to periodically refresh the charge stored in the capacitors. Since a capacitor can store only a very limited amount of charge, in order to quickly distinguish the difference between a logic HIGH and a logic LOW, two bit lines (BLs) are typically used for each bit, wherein the first bit line in the bit line pair is known as a bit line true (BLT) and the other bit line in the bit line pair is the bit line complement (BLC). The single NMOS transistor's gate is controlled by a word line (WL).
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.